The present invention relates to oscillator circuits, and particularly to low-power frequency-stable oscillator circuits configured using CMOS integrated circuit technology, and to systems which use such oscillators for timing functions.
In many system applications, it is desired to provide an oscillator which will run with extreme frequency precision on extremely low power. Some examples of such applications include uninterruptible clock/calendar subsystems, electronic watches and other consumer products, portable measuring equipment, portable communications equipment, and systems for space environments. However, these two demands are to some extent incompatible, in that circuit solutions which tend to improve one of these two parameters tend to degrade the other. The present invention is particularly aimed at systems where both of these requirements must be satisfied.
In most systems where precise frequency control is needed at reasonable cost, a quartz-crystal-controlled oscillator will be used. Quartz crystals can be bought with a sharply tuned resonance frequency. Such a crystal can be used to provide a very sharp resonance in the feedback path of the oscillator, and thereby stabilize the frequency of the oscillator.
One known circuit configuration which can be used for low-power frequency-stabilized oscillators is a Pierce oscillator, in which the crystal is connected across a single-stage CMOS amplifier. To minimize power consumption, a large source resistor is used to provide a virtual ground level for the oscillator which is far above the system ground voltage. In such a circuit, the source resistor will pull up the virtual ground level until it is within approximately one PMOS threshold voltage (V.sub.TP) plus one NMOS threshold voltage (V.sub.TN) below the on-chip positive supply voltage (V.sub.DD). Thus, such a circuit configuration, as long as it operates on extremely low current, will be relatively insensitive to fluctuations in the supply voltage (V.sub.DD), since such fluctuations will tend to change the voltage drop across the source resistor rather than the drop across the circuit. (However, such a circuit will obviously be sensitive to variations in current draw, which would cause the voltage across the source resistor to vary.) Thus, in such a configuration, the voltage of the circuit nodes will tend to be set by the device threshold voltages, while the current draw is controlled by the source resistor.
In such circuit configurations, it is preferable to take the feed for the first output buffer stage from the input side of the amplifier. This avoids degrading the loop gain of the amplifier plus resonator. In environments where such a circuit may have to cope with fluctuating supply voltage as described, the bias point for the input from the amplifier to the following stages must be set correctly. For example, it is possible for some circuits of this type to operate in a mode wherein oscillation is occurring at the amplifier, but no signal appears at the output of the output buffer, since an incorrect bias level has swamped the AC signal at the input to the output buffer. In such circuits, an appropriate bias level for inter-stage inputs can be provided by using a transmission gate (with long-channel NMOS and PMOS transistors in parallel) to partly couple the output side of the amplifier across to the input side of the amplifier. If the N-channel and P-channel threshold voltages have approximately equal magnitude, the inverter stage will have almost no net body effect; but the transmission gate will have significant body effect, so that the effective threshold voltages of the devices in the transmission gate are increased slightly in magnitude. Therefore, even though the gates of the devices in the transmission gate are tied to V.sub.DD and V.sub.SSH1, the transmission gate will be barely off if the bias at node B (as shown in FIG. 1) is optimal. However, if the bias point needs to be shifted, the transmission gate 130 will pass charge accordingly.
Since the preferred circuit configuration for such applications uses only a very minimal number of stages, without extensive buffering to isolate nodes from each other, this configuration is less stable than some others. That is, parameter variation at one node may affect the behavior of other nodes. In such a circuit configuration, since the drop across the active elements is essentially defined by the device threshold voltages, process-induced variations in the threshold voltages can significantly affect the voltage drops seen. For example, where both N-channel and P-channel threshold voltages V.sub.TN and V.sub.TP are specified at 0.75.+-.0.25 volts, the effective power supply voltage difference across the oscillator may be anywhere from one to two volts, i.e. a 2:1 variation is possible. In fact, this variation in threshold voltages may cause as much as a 3:1 variation in current, and change the loop gain of the oscillator.
A problem which has been discovered with such circuits is current diversion when the oscillator is started up. To better understand this problem, the concept of the "trip point" of a circuit stage will first be explained.
The solid-line curve of FIG. 6 is a typical curve of output voltage (V.sub.out) versus input voltage (V.sub.in) behavior of an inverter stage for a typical MOS inverter circuit. As this graph shows, the output voltage of an inverter will shift rapidly when the input voltage reaches voltages close to the trip voltage V.sub.trip, from a voltage near a first power supply V.sub.DD to a voltage near a second power supply V.sub.SS. This curve is typical of a digital circuit (such as an inverter), but the same concept can also be applied to some (but not all) analog circuits. In some nonlinear analog circuits (such as the amplifier stage 110 in FIG. 1), a plot of V.sub.out versus V.sub.in will show maximum steepness near an intermediate input voltage, which may be referred to here as the trip voltage V.sub.trip.
The dotted line in FIG. 6 shows how these characteristics can be modified. For example, the trip voltage of an inverter can be shifted by changing the ratio of the channel lengths of the PMOS and NMOS devices. For example, the dotted line curve of FIG. 6 shows an alternative inverter circuit with a somewhat lower trip voltage. Such a lower trip voltage could be produced by shortening the length of the n-channel pull-down transistor. For example, if the first buffer stage 140 has a curve corresponding to the solid line in FIG. 6, then the modified first buffer stage 240 shown in FIG. 2, wherein the n-channel device has a shorter channel length, might produce an inverter curve as shown in the dashed line of FIG. 6.
When the oscillator starts up, the gain stage of the oscillator is expected to be biased at its trip voltage. However, if the buffer stages have the same trip voltage, and are biased at their trip voltages, current will be diverted through those stages (since the following stages will normally have transistors with shorter channel lengths). This may mean that, at turn on time, the available current (which is limited by the source resistor) flows almost entirely through the buffer stages, and not through the oscillator. For example, in a configuration where the source resistor limits the total current to about 120 nanoamps, it has been found that, in such a condition, the current through the active devices of the oscillator may be as little as one or two nanoamps.
If the current through the oscillator is very small, the oscillator may not be able to begin oscillation. That is, a second order effect in low-power CMOS integrated circuits is that the gain of a circuit stage will be reduced if the current available to that stage is sufficiently limited. In the example just given, if the oscillator can only draw one or two nanoamps, the instantaneous loop gain may not be high enough to begin oscillation. Therefore, in such a condition the oscillator may simply stay in a "stuck" condition.
In fact, it has been experimentally discovered that, if the design trip voltage of the gain stage in the amplifier and of the following inverter stages are equal, then the onset of oscillation can be determined solely by externally generated electrical noise. (The electrical noise may be sufficient to bring the oscillator to an operating point where its loop gain exceeds unity, so that oscillation can thereafter be maintained.) This produces an undesirable degree of unreliability. This is particularly true since the testers normally used to test integrated circuits tend to be high-noise environments. Thus, integrated circuits which will reliably begin oscillation in a tester (due to the high electrical noise levels) may be unable to begin oscillation in an actual service environment. This is very undesirable.
This problem of hang-up can be avoided by designing the inverter and the following buffer stage to have unequal trip voltages. FIG. 2 is an embodiment of this kind. Since n-channel device 244 has a shorter channel length than the p-channel pull up 242, transistor 244 will turn on when the oscillator's gain stage 210 is still at its trip point. (That is, with device dimensions as shown, the trip voltage of the first buffer stage 240 is lower than that of gain stage 210.) This assures that node D will be low, and therefore also assures that buffer stages 240, 150, and 160 will not consume large amounts of current.
However, schemes of this type have a further limitation. In a low-power circuit, it is desirable to keep the operating current as low as possible. Thus, the value of the source resistor is chosen to be high enough that the amplitude of the signal at the input to the first buffer stage is quite small. However, if the first buffer stage has a trip voltage which is not exactly equal to the trip voltage of the gain stage in the oscillator, there will be some risk that the bias signal (which is defined by the operating characteristics of the oscillator) may be inappropriate for the first buffer stage. In fact, if the trip voltage of the first buffer is too different from the trip voltage of the gain stage in the oscillator, it is possible that the AC signal at the input to the first buffer stage may be entirely swamped. That is, the larger the difference in trip voltages between the gain stage of the amplifier and the first buffer stage, the larger magnitude of signal must be supplied at the input to the buffer stage. This in turn implies that the gain stage to the oscillator will require more current draw, and therefore will consume more power, which is undesirable.
Thus, according to this (novel) analysis of the characteristics of such a circuit, it is desirable that the trip voltages of the oscillator gain stage and of the first buffer stage be exactly equal when the oscillator is running, but be different when the oscillator is starting up.
The present invention introduces additional circuit elements which cause the effective trip voltage of the first buffer stage to be dynamically modified. In the presently preferred embodiment, this is done by adding an additional PMOS transistor, with an increased channel length, to the first output buffer stage.
It should also be noted that, less preferably, other device structures could be used to shift the trip voltage of the first buffer stage dynamically. For example, a dual-gate FET structure could be used to accomplish this. Alternatively, a FET structure could be used wherein the channel was both front-gated and back-gated. Alternatively, a stacked gate structure could be used (physically somewhat analogous to conventional EPROM device structures) where charge stored in one electrode causes the effective gate voltage seen by a second electrode to change.
The effect of the longer channel length is to slightly shift the threshold voltage of the device (and therefore the trip voltage of the circuit stage). For example, in an alternative embodiment wherein the PMOS pass transistor 146 (as shown in FIG. 1) is 30 microns wide and 16 microns long, and the transistors 112 and 114 of the oscillator gain stage are both 12 microns long, a simulation of a sample set of process conditions indicated a threshold voltage V.sub.TP of 1.2231 for the PMOS pass transistor 146, and a threshold voltage V.sub.TP equals 1.2164 for the pull-up transistor 112 in the oscillator gain stage 110. This seven milliVolt difference in threshold voltages corresponds to current draws, at the bias point, of 72 nanoamps through the oscillator 110 and 20 nanoamps through the first buffer stage 140. Thus, the 7 milliVolt threshold shift in the p-channel pass transistor 146 has the effect of diverting the majority of current into the oscillator gain stage, as desired.
The use of even longer transistor channel lengths can produce additional shift in threshold voltage (and hence in the trip voltage of the resulting circuit). However, it should be noted that successively less change in threshold voltage is produced by a given increase in channel length, at longer channel lengths.
In the presently preferred embodiment, the CMOS amplifier stage has quite long transistors. In the presently preferred embodiment, using two micron technology, the transistors of this amplifier stage have 12 micron channel lengths. These long channel lengths effectively increase the threshold voltage of these transistors by about 15 milliVolts.
As noted, in the presently preferred embodiment, a pass transistor is added in the first stage of the output buffer. Where the source resistor is placed on the negative (ground) side of the circuit, this added pass transistor is placed on the upper leg of the first stage output buffer, and is preferably PMOS. A simple digital signal is used to switch the gate voltage of this PMOS pass transistor between two possible signals. In one mode (e.g. at startup), the gate of this long and wide PMOS pass transistor is connected, in common with the gates with the PMOS and NMOS load and driver transistors in this stage, to the signal across the crystal. Since this pass transistor is substantially longer than the transistors in the amplifier stage, the series combination of the PMOS load and pass transistors (in the first stage of the output buffer) will pass much less current than the PMOS pull-up transistor in the amplifier, when these transistors are all biased near cut off. (That is, when transistors 112 and 142 are just turning on, transistor 146 will still be fairly well turned off.) Thus, in this mode the majority of the operating current will go through the amplifier stage. This assures a reliable turn-on of the oscillation. In a second operating mode, the PMOS pass transistor is turned hard on. Since this device is quite wide, in this mode it simply connects the PMOS pull-up transistor directly to the positive power supply. Thus, the lengths of the PMOS load and NMOS driver in the first stage of the output buffer can be selected for optimal operation in this mode. Thus, this circuit configuration provides extreme stability in the oscillator, and also provides a reliable good match between the oscillator and the output buffer, without degrading the power efficiency of the circuit.
An advantage which results from this is that the devices can be optimized to achieve the best performance in the run mode. In particular, the trip voltages of the output buffer stages can be made as nearly as possible equal to the trip voltage of the amplifier gain stage. This in turn means that the circuit can be operated down to lower levels of supply voltage V.sub.DD, which is desirable.
According to the present invention there is provided: An integrated circuit oscillator, comprising: first and second resonator leads connectable to a resonator; first and second local power supply leads, at least one of the local power supply leads being connected through a resistance to a system power supply lead; an amplifier stage operatively connected to provide AC amplification between the first and second resonator leads, and operatively connected to be powered by the local first and second power supply leads; a first-stage output buffer, operatively connected to be powered by the local first and second power supply leads, including an output node, and a gain stage which an input connected to the amplifier stage and which is connected to drive the output node toward the voltage of one of the power supply leads selectively in accordance with the voltage received from the amplifier stage, wherein the gain stage is controlled by logic so that, in a first mode, the gain stage has a significantly lower conductance, at equal input voltages, than the amplifier stage, and, in a second mode, the gain stage has a significantly lower conductance, at equal input voltages, than the amplifier stage.
According to the present invention there is provided: An integrated circuit oscillator, comprising: first and second leads connectable to a resonator; an amplifier stage having an output side operatively connected to the first lead and an input side operatively connected to the second lead; an output buffer, having an input lead operatively connected to receive an AC signal from the input side of the amplifier stage, and connected to receive a quasi-DC signal from the output side of the amplifier stage; a bias feedback path, which provides a quasi-DC signal from the output side of the amplifier back to the input of the output buffer; first and second local power supply leads, at least one of the local power supply leads being connected through a resistance to a system power supply lead; wherein the output buffer comprises a first stage having an output node, a first active device, which has an input connected to the amplifier stage and which is connected to drive the output node toward the voltage of the first power supply lead selectively in accordance with the voltage received from the amplifier stage, a second active device, which has an input connected to the amplifier stage and which is connected to drive the output node toward the voltage of the second power supply lead selectively in accordance with the voltage received from the amplifier stage, a third active device, which is interposed between the first active device and the first local power supply lead, and which has an input controlled by logic so that, in a first mode, the input of the third active device is connected in parallel with the input of the first active device, and, in a second mode, the third device remains in a low-impedance condition, and which has a significantly higher impedance than the first active device, at input voltages where the first active device is just beginning to turn on.
According to the present invention there is provided: an integrated circuit oscillator, comprising: first and second leads connectable to a resonator; an amplifier stage having an output side operatively connected to the first lead and an input side operatively connected to the second lead; an output buffer, having an input lead operatively connected to the amplifier stage; a bias feedback path, which provides a quasi-DC signal from the output side of the amplifier back to the input of the output buffer; first and second local power supply leads, at least one of the local power supply leads being connected through a resistance to a system power supply lead; wherein the output buffer comprises a first stage having an NMOS driver transistor, a PMOS load transistor, and a PMOS pass transistor operatively connected in series between the first and second local power supply leads, the gates of the driver and load transistors being connected to the input lead of the buffer, wherein the pass transistor has a much lower conductance than the load transistor at equal small-signal gate voltages, and a second stage having an input connected to a node between the driver and load transistors of the first stage.
According to the present invention there is also provided: An integrated circuit oscillator, comprising: first and second leads connectable to a resonator; an amplifier stage having an output side operatively connected to the first lead and an input side operatively connected to the second lead; an output buffer, having an input lead operatively connected to receive an AC signal from the input side of the amplifier stage, and connected to receive a quasi-DC signal from the output side of the amplifier stage; a bias feedback path, which provides a quasi-DC signal from the output side of the amplifier back to the input of the output buffer; first and second local power supply leads, at least one of the local power supply leads being connected through a resistance to a system power supply lead; wherein the output buffer comprises a first stage having an NMOS driver transistor, a PMOS load transistor, and a PMOS pass transistor operatively connected in series between the first and second local power supply leads, the gates of the driver and load transistors being connected to the input lead of the buffer, wherein the pass transistor has a channel length which is much longer than that of the load transistor, and a second stage having an input connected to a node between the driver and load transistors of the first stage.
According to the present invention there is also provided: An integrated circuit oscillator, comprising: first and second leads connectable to a resonator; an amplifier stage, comprising a PMOS pull-up transistor and an NMOS pull-down transistor, and having an output side operatively connected to the first lead and an input side operatively connected to the second lead; an output buffer, having an input lead operatively connected to receive an AC signal from the input side of the amplifier stage, and connected to receive a quasi-DC signal from the output side of the amplifier stage; a bias feedback path, which provides a quasi-DC signal from the output side of the amplifier back to the input of the output buffer; first and second local power supply leads, at least one of the local power supply leads being connected through a resistance to a system power supply lead; wherein the output buffer comprises a first stage having an NMOS driver transistor, a PMOS load transistor, and a PMOS pass transistor operatively connected in series between the first and second local power supply leads, the gates of the driver and load transistors being connected to the input lead of the buffer, wherein the pass transistor has a channel length which is much longer than that of the pull-up transistor of the amplifier, and a second stage having an input connected to a node between the driver and load transistors of the first stage.
According to the present invention there is also provided: An integrated circuit oscillator, comprising: first and second leads connectable to a resonator; first and second local power supply leads, at least one of the local power supply leads being connected through a resistance to a system power supply lead; an amplifier stage, comprising an NMOS pull-down transistor and a PMOS pull-up transistor connected in series between the first and second local power supply leads; an output buffer, having an input lead operatively connected to the amplifier stage, wherein a first stage of the output buffer comprises an NMOS driver transistor and a PMOS load transistor operatively connected in series between the first and second local power supply leads; and a bias feedback path, which provides a quasi-DC signal from the output side of the amplifier back to the input of the output buffer; and wherein the quantity LP1/LN1 is at least 20% greater than the quantity LP2/LN2, where LN2 is the channel length of the pull-down transistor of the amplifier, LP2 is the channel length of the pull-up transistor of the amplifier, LN1 is the channel length of the driver transistor of the first stage of the buffer, and LP1 is the channel length of the load transistor of the first stage of the buffer.